The present invention relates to semiconductor processing. Specifically, the present invention relates to a process and apparatus for producing phosphosilicate glass having a high wet-etch rate ideally suited for manufacturing integrated circuits.
In the current evolution of integrated circuits there exists a constant drive to reduce the per unit cost of the circuits. This has led to a great increase in circuit density on a given substrate, and a reduction in the size of the circuit's features. However, reducing the feature size of certain integrated circuits poses significant challenges due to the electrical characteristics of the same. For example, reducing the feature dimensions of the storage capacitors associated with dynamic random access memory (DRAM) integrated circuits poses a significant challenge.
A typical DRAM consists of an array of individual cells, each of which stores a unit of data (bit) and includes a charge-passing transistor and a storage capacitor. As shown in FIG. 1, a typical prior art cylindrically shaped storage capacitor, associated with a DRAM device, is formed on a semiconductor substrate 11 having disposed thereon a field oxide region 12 for device isolation, a gate oxide layer 13, a gate electrode 14 and source/drain regions 15. Atop the aforementioned structure is an interlayer insulation film 16 having a bit line 17 formed therein. To form the storage capacitor, a planarization layer 18 is formed atop both the bit line and the insulation film 16. The planarization layer 18 typically consists of borophosphosilicate glass (BPSG). An oxide layer 19 is formed atop of the planarization layer 18. Thereafter, the oxide layer 19, the planarization layer 18 and the interlayer insulation film 16 are, in sequence, removed at an area where the storage electrode contact is to be formed, defming a storage electrode contact hole 20. A first polysilicon layer is deposited to fill the contact hole 20, followed by formation of a sacrificial layer 22 on the polysilicon of the contact hole 20. The sacrificial layer 22 is formed from an oxide and functions as a mask so that the first polysilicon layer may be etched to form a first polysilicon pattern 21.
Referring to FIG. 2, a second polysilicon layer 23 is formed. The second polysilicon layer 23 covers the oxide layer 19, sacrificial layer 22, and the first polysilicon pattern 21.
Referring to FIG. 3, the second polysilicon layer 23 is subjected to anisotropic etch which removes the sacrificial layer 22 and the oxide 19 to form a polyspacer 24. As a result, a cylindrical storage electrode 25 is formed consisting of the polysilicon pattern 21 and the polyspacer 24.
Reducing the size of the capacitor has deleterious affects on the proper functioning of the DRAM device. The proper functioning of the DRAM integrated circuit requires that the capacitor obtain a sufficient charge to maintain an acceptable signal-to-noise ratio. The charge a capacitor can store is proportional to the capacitor's size. These factors place a significant limit on the reduction in size of the storage capacitor, thereby limiting the reduction in per unit cost of the DRAM. As a result, storage capacitors on a DRAM device occupy most of the device's area. U.S. Pat. Nos. 5,478,769; 5,480,824; 5,482,886; 5,501,998 each describes prior art attempts to reduce the overall size of the storage capacitor, while maintaining, or increasing, the charge per unit area stored thereby. A drawback with the prior art attempts to reduce the size of the storage capacitor is that each increases the time and complexity of the processes for manufacturing the storage capacitor.
Other attempts to reduce the per unit cost of integrated circuits has focused on a reduction in processing time. One such attempt includes forming certain layers, such as sacrificial layer 22, from materials having a high etch rate. This decreases the time necessary to remove the layer, thereby reducing the time necessary to manufacture the integrated circuit. An important characteristic of sacrificial layers is that they be deposited with a substantially uniform thickness. This facilitates control of the feature dimensions and, therefore, operation of the device once constructed. However, sacrificial layers of the prior art typically suffer from either poor thickness uniformity or poor etch rates.
What is needed, therefore, is a process and apparatus that reduces the time required to manufacture an integrated circuit by providing a sacrificial layer having improved etch rate characteristics and thickness uniformity.